A semiconductor device includes a data output driver which outputs data to the outside in an output operation. The data output driver drives data to a target voltage and then output the driven data, considering a loading of a data transmission path.
A slew rate refers to the degree of voltage variation during a time taken until data driven by the data output driver reaches a target voltage. The slew rate represents how fast a voltage level of an output signal changes, that is, a slope of a voltage graph with respect to time. The slew rate may be classified into an up slew rate and a down slew rate. The up slew rate refers to a slope when an output voltage level changes from a low level to a high level, and the down slew rate refers to a slope when an output voltage level changes from a high level to a low level. As the slew rate is higher, an absolute value of the voltage graph becomes larger. This means that the output voltage level rapidly changes in a short time.
FIG. 1 is a block diagram of a known output driver.
As illustrated in FIG. 1, the known output driver includes a driving signal generation unit 1 and a driving unit 2. The driving signal generation unit 1 is configured to receive input data Din and generate first to third pull-up signals PU<1:3> and first to third pull-down signals PD<1:3> in response to first to third driving strength signals STCTRL<1:3>. The driving unit 2 is configured to drive output data Dout in response to the first to third pull-up signals PU<1:3> and the first to third pull-down signals PD<1:3>.
As illustrated in FIG. 2, the driving unit 2 includes a PMOS transistor P1, an NMOS transistor N1, a PMOS transistor P2, an NMOS transistor N2, a PMOS transistor P3, and an NMOS transistor N3. The PMOS transistor P1 is configured to pull up the voltage of the output data Dout in response to the first pull-up signal PU<1>. The NMOS transistor N1 is configured to pull down the voltage of the output data Dout in response to the first pull-down signal PD<1>. The PMOS transistor P2 is configured to pull up the voltage of the output data Dout in response to the second pull-up signal PU<2>. The NMOS transistor N2 is configured to pull down the voltage of the output data Dout in response to the second pull-down signal PD<2>. The PMOS transistor P3 is configured to pull up the voltage of the output data Dout in response to the third pull-up signal PU<3>. The NMOS transistor N3 is configured to pull down the voltage of the output data Dout in response to the third pull-down signal PD<3>. Among the PMOS transistors P1 to P3, the PMOS transistor P3 has the largest size and the PMOS transistor P1 has the smallest size. In addition, among the NMOS transistors N1 to N3, the NMOS transistor N3 has the largest size and the NMOS transistor N1 has the smallest size.
The first to third driving strength signals STCTRL<1:3> are set by a mode register set, and the driving strength of the output driver is adjusted to one of “FULL”, “HALF”, and “WEAK” according to the first to third driving strength signals STCTRL<1:3>. The operation of adjusting the driving strength of the output driver according to the first to third driving strength signals STCTRL<1:3> will be described below in detail.
When the first driving strength signal STCTRL<1> is enabled to a logic high level and the input data Din is at a logic high level, the first pull-up signal PU<1> is enabled to a logic low level. When the input data Din is at a logic low level, the first pull-down signal PD<1> is enabled to a logic high level. Therefore, when the input data Din is at a logic high level, the PMOS transistor P1 of the driving unit 2 becomes turned on, and drives the output data Dout. When the input data Din is at a logic low level, the NMOS transistor N1 of the driving unit 2 becomes turned on, and drives the output data Dout. Since the PMOS transistor P1 among the PMOS transistors P1 to P3 has the smallest size and the NMOS transistor N1 among the NMOS transistors N1 to N3 has the smallest size, the driving unit 2 drives the output data Dout with the weakest driving strength “WEAK” when the first driving strength signal STCTRL<1> is enabled to a logic high level.
Next, when the second driving strength signal STCTRL<2> is enabled to a logic high level and the input data Din is at a logic high level, the second pull-up signal PU<2> is enabled to a logic low level. When the input data Din is at a logic low level, the second pull-down signal PD<2> is enabled to a logic high level. Therefore, when the input data Din is at a logic high level, the PMOS transistor P2 of the driving unit 2 becomes turned on, and drives the output data Dout. When the input data Din is at a logic low level, the NMOS transistor N2 of the driving unit 2 becomes turned on, and drives the output data Dout. Since the PMOS transistor P2 is larger than the PMOS transistor P1 and smaller than the PMOS transistor P3 and the NMOS transistor N2 is larger than the NMOS transistor N1 and smaller than the NMOS transistor N3, the driving unit 2 drives the output data Dout with the driving strength “HALF” higher than “WEAK” and lower than “FULL”, when the second driving strength signal STCTRL<2> is enabled to a logic high level.
Next, when the third driving strength signal STCTRL<3> is enabled to a logic high level and the input data Din is at a logic high level, the third pull-up signal PU<3> is enabled to a logic low level. When the input data Din is at a logic low level, the third pull-down signal PD<3> is enabled to a logic high level. Therefore, when the input data Din is at a logic high level, the PMOS transistor P3 of the driving unit 2 becomes turned on, and drives the output data Dout. When the input data Din is at a logic low level, the NMOS transistor N3 of the driving unit 2 becomes turned on, and drives the output data Dout. Since the PMOS transistor P3 among the PMOS transistors P1 to P3 has the largest size and the NMOS transistor N3 among the NMOS transistors N1 to N3 has the largest size, the driving unit 2 drives the output data Dout with the strongest driving strength “FULL” when the third driving strength signal STCTRL<3> is enabled to a logic high level.
As described above, the known output driver drives the output data with the driving strength adjusted by the first to third driving strength signals STCTRL<1:3> set by the mode register set. Therefore, the slew rate of the output data Dout is also adjusted by the first to third driving strength signals STCTRL<1:3>.
However, when the level of the power supply voltage VDD changes, the driving strength of the output driver supplied with the power supply voltage VDD may change and thus the slew rate of the output data Dout may be influenced. For example, even though the third driving strength signal STCTRL<3> is set to a logic high level, and thus the driving strength of the output driver is set to “FULL”, the driving strength of the output driver may decrease if the level of the power supply voltage VDD is low. Consequently, the slew rate of the output data Dout may also decrease. The reduction of the slew rate according to the level of the power supply voltage VDD may cause distortion in the waveform of the output data Dout.